1. Field of the invention
The invention relates to a circuit for producing a data bit inversion flag for the purpose of data inversion for a data burst which has been read from a memory chip, in particular for DDR-SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories).
2. Description of the Prior Art
FIG. 1 shows a computer system based on the prior art in which a memory chip and a controller chip interchange data via a common data bus. The increasing speed of computer processors or controllers requires a correspondingly higher speed for memory access operations or faster memory chips. The memory chip and the processor are clocked by means of a clock signal CLK.
Various generations of RAM stores have been developed, whose access rate rose constantly. The intervals of time in which new data which are read from the memory cell array or which are to be written are available at the data inputs/outputs of the memory chip in question were constantly shortened during this time. Taking synchronous dynamic RAMs (SDRAMs) as a basis, what are known as DDR-SDRAMs were developed, which have double the data rate. Such DDR-SDRAMs deliver data twice as quickly as conventional SDRAMs. DDR-SDRAMs do not double the clock rate, however, but rather two actions are executed in one clock cycle. Whereas conventional SDRAMs are always synchronized only to the rising clock edge of the bus clock, a DDR-SDRAM uses both the rising clock edge and the falling clock edge for data and command transmission.
The data transmission rate of the DDR-SDRAM, which corresponds to a double clock frequency, is almost 2 GHz for clock frequencies in the range from 800 MHz to 1 GHz.
During read access to the memory chip, data are read as a data burst, each data burst comprising a plurality of data words which each comprise a predetermined number n of data bits. The number of data bits within a data word corresponds to the bus width N of the data bus. In one data burst, for example, 4 data bits (m=4) each comprising 8 bits (n=8) are read. FIG. 2 shows the reading of a data burst from an SDRAM based on the prior art. The increasing operating frequency means that the inductive and capacitive coupling is increased, so that data corruptions arise. As the operating frequency increases, it becomes ever more difficult to transmit the data from the memory chip to the controller. A limitation in this context is the noise on the data lines of the data bus. The noise limits the validity period of the data and reduces the “data eye size”. The more switching operations or data transitions occur on the data lines, the more the data corruptions increase, i.e. the bit error rate (BER) rises.
FIG. 3 shows the transmission of a data burst during a read access operation from a memory chip to a controller in a conventional data processing system based on the prior art. In the example shown in FIG. 3, a data burst containing 8 data words each comprising 8 bits is transmitted. When the memory chip has received a read instruction RD from the controller via a control bus, it transmits a data burst to the controller via the data bus after a certain latency. In the example shown, the memory chip transmits the following sequence of data words, namely: FF, 00, 00, EF, FF, 00, 02, FF. FIG. 3 indicates the number of bits arising in this context which change their value when moving from one data word to the next data word.
When moving from the first data word (FF) to the second data word (00), all the bits in the data word change their logic value. In the case of the next transition, none of the bits changes its logic value. When moving from the data word 00 to the data word EF, seven bits change their logic value.
To limit the noise caused by the switching, the GDDR4 (Graphics Data Double Rate) standard introduces what is known as data bit inversion (DBI). In this case, before the data are transmitted, a decoder is used internally in the memory chip to check how many data bits in a data word have changed relative to the data bit transmitted directly beforehand in the preceding data word. If the number of data bits which have changed exceeds half of the data bits in the data word, all the data bits in the subsequent data word are transmitted to the controller on the data bus in inverted form. The inversion of the data bits in the data word is indicated to the controller by additional transmission of a DBI flag. FIG. 4 shows such data bit inversion based on the prior art and for the example shown in FIG. 3.
Since more than half, namely, eight data bits change data state between the first two data words (FF, 00), the second data word is transmitted in inverted form as FF. Since likewise more than half of the data bits change their state between the inverted data word FF and the next data word 00 which is to be transmitted, the third data word is also transmitted to the controller in inverted form and as FF. Since only one data bit transition and hence less than half the number of data bits within a data word is inverted between the third inverted transmitted data word and the next data word EF to be transmitted, the fourth data word EF is transmitted to the controller in uninverted form etc. As can be seen from FIG. 4, the number of data bit transitions or switching bits is much smaller than in the case of a data transmission without data bit inversion, as shown in FIG. 3. FIG. 4 also shows the data bit inversion flag DBI transmitted in parallel, which indicates to the processor whether or not the received data word has been inverted.
FIG. 5 shows a circuit unit for data bit inversion in a data burst which has been read from a memory chip, based on the prior art. From the memory cell array, the entire data burst which has been read is first of all buffer-stored in a burst buffer store. By way of example, the burst buffer store is used to buffer-store m=4 data words each containing n=8 data bits. For each data word DW within the burst buffer store, an associated decoder is provided, for example m=4 decoders. Each decoder compares the data bits in a data word with those data bits in the preceding data word.
FIG. 6a shows a circuit design for a conventional decoder, as is used in the data bit inversion unit based on the prior art shown in FIG. 5. The data word which has been read from the burst buffer store is loaded into a register when an ENABLE signal (EN) is received.
At the same time, the preceding data word (DWi-1) in the data burst is likewise loaded into a register as a reference data word. FIG. 6b shows a conventional circuit arrangement for a DBI decision circuit based on the prior art. An XOR logic circuit compares the data content of the two registers bit by bit. A counting device counts the number of different data bits. A comparator compares the number of different data bits in the two data words with half the number of data bits within a data word. If the number of data bits within a data word is 8 bits, for example, the comparator compares the rounded-up number of different data bits with the value 4. If the number of different data bits is greater than half the number n of data bits within the data word, a data bit inversion flag (DBI) is set by the comparator. The DBI flag controls a multiplexer in the decoder internally. The data word DWi buffer-stored in the first register is switched through by the multiplexer either in inverted form or in uninverted form. When the comparator sets the DBI flag, there follows bit-by-bit inversion of the data bits. Once the comparator has finished the comparison, it forwards a READY indicator control signal to the next decoder within the cascade.
As can be seen from FIG. 5, the data words DW which are output by the decoders are applied to a parallel/serial converter which is activated by the READY control signal from the last decoder within the cascade. The parallel/serial converter converts the received data words and the associated data bit inversion flags into a serial data stream. A data bus is used to output a data burst comprising m data words, which each have a bit length n, and also m data bit inversion flags to the controller. As can be seen from FIG. 5, the decoders in the data bit inversion unit based on the prior art operate in serial fashion. The decoders are connected up as a cascade, i.e. a decoder I within the cascade always requires the output value from the preceding decoder i-1 within the cascade as reference data word in order to be able to make the necessary comparison. The parallel/serial converter P/S cannot start to convert the data words available in parallel form into a serial sequence until after the last decoder DECm within the cascade has finished the comparison and activates it by means of an ENABLE signal. The waiting time is thus m times the necessary decoding time for a decoder i within the cascade:Twait=m TDEC
If the decoding time for a decoder DECi within the cascade is 1 nanosecond, for example, and if a data burst comprises m=4 data words then the waiting time is 4 ns.
The increased waiting time results in an unwanted delay in the memory access time for data within the memory chip. This has an overall negative effect on the system performance. The serial processing during the DBI assessment results in a long time delay for the parallel data transmission, since it is necessary to wait until the decoding of the last data word within the data burst has ended. All the data which have already been processed have to wait this time until they can be processed further in parallel.
FIG. 6c shows an alternative conventional circuit arrangement for a DBI decision circuit within a decoder based on the prior art. In this conventional DBI decision circuit, the different data bits which an EXOR circuit detects between two adjacent data words are supplied to a memory in which a table is stored. For each of the 2n possible values, the stored table contains an associated data bit inversion flag value. If the number n of data bits within a data word DW is 8 bits, for example, then there are 28=256 possible combinations. For each combination for which the number of data bits having the value 1 is more than half n/2 the number n=8 of data bits within the data word, the stored data bit inversion flag DBI has a logic high value. Conversely, for each combination for which the number of logic high data bits is less than half the number n of data bits within a data word DW, the associated data bit inversion flag DBI is stored with the value 0. The memory thus forms a full decoder for all 2n bit combinations. The memory may be replaced by a logic circuit.
Both the data bit inversion decision circuit shown in FIG. 6b and the data bit inversion decision circuit shown in FIG. 6c based on the prior art are relatively slow. The necessary time for producing the data bit inversion flag DBI is thus relatively long, which means that the memory access time for accessing the memory chip is increased overall.
A further drawback of the conventional data bit inversion decision circuits shown in FIGS. 6b and 6c is that the circuit complexity is likewise relatively high, which means that the chip area required for integration of a semiconductor chip is large. This increases the costs of implementation.
It is an object of the present invention to provide a circuit for producing a data bit inversion flag in which the time required for producing the data bit inversion flag is minimal, which means that the memory access time is reduced.
The object is achieved in accordance with the invention by means of a circuit for producing a data bit inversion flag, having:
a first summed-current production unit for producing a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent data words in a data burst,
a second summed-current production unit for producing a second summed current, whose amplitude is proportional to the number of identical data bits in the two adjacent data words in the data burst; and having
a current comparator which compares the two summed currents produced with one another and produces the data bit inversion flag if the first summed current is larger than the second summed current.
The inventive circuit for producing a data bit inversion flag may be preferably of purely analogue design. In comparison with the conventional DBI decision circuit, this avoids counting the EXOR results, which takes at least n clock cycles. The inventive circuit thus operates considerably more quickly.
In comparison with the conventional DBI decision circuit with full decoding, as shown in FIG. 6c, the inventive circuit avoids the relatively slow addressing and reading from a memory and the long signal propagation times which are required for an implementation with a logic gate. The inventive DBI decision circuit is thus much faster and, on account of the low circuit complexity, requires far less area for integration on a chip.
The idea on which the inventive circuit and the inventive method are based is to compare the number of different data bits in two adjacent data words in a data burst and the number of identical data bits in the two adjacent data words in the data burst with one another using a current balance.
The two summed-current production units may each be formed from transistors connected in parallel which are switched on the basis of the data bits.
Particularly, two adjacent data words may each be provided with an added supplementary data bit which has a firmly prescribed logic value, so that the number n of data bits within a data word is always uneven. By adding such a supplementary data bit with a fixed logic value, for example with a logic value 1, a certain decision is made even if the number of different data bits between two adjacent data words DW is precisely n/2. If the data words each comprise 8 bits, for example, and if precisely 4 bits of the two adjacent data words are unequal, then without adding a supplementary data bit the current balance would not swing distinctly in favour of inversion or noninversion.
The current comparator may be formed by a differential amplifier. This current comparator is preferably likewise of purely analogue design but delivers a digital result in the form of a data bit inversion flag.
The current comparator may be a clocked current comparator which is clocked by a data clock signal. This has the particular advantage that the current drawn by the inventive circuit for producing a data bit inversion flag is reduced overall, because clocked current comparators generally operate more quickly and draw no static current.
The current comparator may contain two inversion stages which each comprise two complementary transistors. The two complementary transistors in the first inversion stage may be connected to one another at a first node and the two complementary transistors in the second inversion stage may be connected to one another at a second node.
The invention circuit may be activated by a start control signal.
The current comparator may be connected to the first summed-current production unit at a third node and to the second summed-current production unit at a fourth node. The third node and the fourth node may particularly be shorted by means of at least one transistor when the inventive circuit has been deactivated.
The first node and the second node may held at a prescribed supply potential in the deactivated state of the inventive circuit by means of a PULL-UP circuit, the PULL-UP circuit may have transistors which are switched on the basis of the start control signal, and the two summed-current production units may be connected to one another at a fifth node.
The fifth node may be connected by a transistor to a prescribed supply voltage potential on the basis of the start control signal.
The data bit inversion flag may be tapped off for output thereof at the first node.
The first node and the second node are connected to a NAND gate for producing a Ready indicator signal (Ready).
The data bit inversion flag produced may control a multiplexer which takes the data bit inversion flag as a basis for switching through the present data word from the two adjacent data words in the data burst in inverted or uninverted form.
The transistors may be formed by MOS field-effect transistors. Particularly the MOS field-effect transistors may be N-MOS field-effect transistors.
The object is also achieved in accordance with the invention by means of a method for producing a data bit inversion flag, having the following steps, namely:                (a) a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent words in a data burst, is produced;        (b) a second summed current, whose amplitude is proportional to the number of identical data bits in two adjacent data words in a data burst, is produced;        (c) the two summed currents produced are compared with one another; and        (d) the data bit inversion flag is produced if the first summed current is larger than the second summed current.        